cmos circuits造句

• On the stability of cmos circuit and silicon controlled rectifier
  电路与可控硅电路的稳定性
• Semiconductor integrated circuits general principles of measuring methods for cmos circuits
  半导体集成电路cmos电路测试方法的基本原理
• This is due to the fact that each transistor in a cmos circuit is actually made from a pmos transistor and an nmos transistor
  这是由于cmos里的每一个晶体管都是由一个pmos和一个nmos晶体管组成的。
• In this paper , a record / playback 1c using adm is designed systematically . the adm algorithm is described and implemented with mixed - signal cmos circuits
  本论文主要设计了一种采用adm编码的语音专用芯片，完成了adm编解码器的原理研究、算法设计和电路实现。
• With the popular sources and models of static power fully discussed at first , the stack effect of transistor - level and logic - level cmos circuits are analyzed in detail according to the broadly adopted uc berkeley bsim model
  这是一款risc指令集的低功耗处理器芯片,它采用哈佛总线结构,兼容了avr指令集,具有4kb片内sram , 128kbflash (暂时处于片外) ,除了
• The constitution and the generation of cmos circuit power were researched , the main method of reducing power was illustrated , and we designed the whole circuit of thermometer according to the rule of low power and high reliability
  研究了cmos电路功耗的组成与产生原因,阐述了降低功耗的主要途径,并按照低功耗、高可靠性要求设计了体温计的整体电路。
• Its intrinsic switching time is very short ; on the order of a picosecond . perhaps even more important is the low power dissipation ; superconducting circuits dissipate on the order of a microwatt per gate , a thousand times less than cmos circuits
  这种数字电子技术具有高速、低功耗的特点，使用基于rsfq技术的逻辑电路的时钟频率可达到几百个ghz ，而功耗只有0 . 3微瓦门。
• According to the redundancy in digital circuits , we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits . to erase the redundant transition of the clock , the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design
  为消除时钟信号的兀余跳变，提出了利用时钟两个方向跳变的双边沿触发器逻辑发计并应用于时序电路设计中。
• Based on the analysis and research on fan algorithm , an iddt test pattern generation algorithm for stuck - open faults is present . in the case of ignoring hazards , for the stuck - open faults in cmos circuits , the feasibility of transient current test generation based on fan algorithm is discussed
  本文采用启发式搜索的方法，基于对fan算法的分析，在不考虑冒险的情况下对于cmos电路中的开路故障，探讨了利用fan算法进行瞬态电流测试生成的可能性。
• The implementation of in - chip clock generator is often based on modern cmos ic process technology which is usually adopted by very large scale digital system . while designing a deep sub - micrometer cmos circuit , delay , power consumption and die size are of the main factors that must be considered
  使用现代深亚微米cmos集成电路工艺制造的内部时钟发生器要综合考虑延时、功耗、面积等各种重要因素，而且经常要针对soc系统的需求设计特殊的电路结构。
• Dynamic power is dominant component of the average power dissipation in cmos circuits . and the value of dynamic power is determined by node capacitance , supply voltage , clock frequency and switching activity of cmos circuits . so most low power designs are achieved by reducing one or more those above parameters
  由于cmos电路的功耗与cmos电路的负载电容，电压，时钟频率及开关活动性有关，因此在低功耗cmos触发器设计过程中，许多低功耗设计技术都可以归结到通过减小上面的参数来达到低功耗的目的。
• In this paper , low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed
  与此相对应的，在本论文中，分别对将少时钟负载或数据通路的负载的触发器设计；减小时钟信号幅度的触发器设计；降低时钟频率的双边沿触发器设计以及应用门控技术来减少触发器无效跳变设计的触发器结构进行了讨论。
• Finally , th e design of low voltage low power current mode cmos circuit is discussed , the design is base on a novel structure which converts serial switches to parallel switches , allows the circuits to perform under lower source voltage which makes low power consuming possible , examples and simulation results are also given to prove the low power character can be reached
  论文最后还讨论了低电压低功耗电流型cmos电路的设计，这一设计巧妙地将电路中的串联开关转换成并联开关，使电流型cmos电路能在更低的电源电压下工作，实现了电路的低功耗设计。论文中给出的设计实例和仿真结果验证了基于并联开关的电流型cmos电路的低功耗特性。
• More recently , the advent of new soi wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on soi for the fabrication of low - power ( lp ) , low - voltage ( lv ) , and high - frequency ( hf ) cmos circuits . in this thesis , we study the electrical characterization on soi wafers and design a low - power soi cmos dram structure
  第二部分我们对高性能低功耗soidram结构的设计进行了研究，设计了一个低压低功耗soidram阵列模型，介绍了我们的dram的逻辑结构设计，存储单元设计，存储器阵列的设计，及读写电路等外围电路的设计。
• Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ) . in this paper , some means to harden the devices against these phenomena are used . guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup
  在本文设计中，采用双环保护结构，大大的降低了cmos集成电路对单粒子闩锁效应的敏感性；对nmos管采用环型栅结构代替传统的双边器件结构，消除了辐射感生边缘寄生晶体管漏电效应；采用附加晶体管的冗余锁存结构，减轻了单粒子翻转效应的影响。
• In the early 1980 ’ s , quiescent power supply current ( iddq ) testing method was proposed in cmos testing . testing method based on current testing have very good compatibility with cmos circuits , it can detect some faults and physical defects those cannot be detected by testing methods based on voltage testing
  基于电流的iddq测试方法与cmos电路有很好的兼容性,它可检测出电压测试方法不能检测的故障和物理缺陷,目前已成为一种广为接受的重要的cmos数字集成电路的测试方法。